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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9990/D Rev 5, 03/2002
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Low Voltage PLL Clock Driver
The MPC9990 is a low voltage PLL clock driver designed for high speed clock generation and distribution in high performance computer, workstation and server applications. The clock driver accepts a LVPECL compatible clock signal and provides 10 low skew, differential HSTL1 compatible outputs, one HSTL compatible output for system synchronization purposes and one HSTL compatible PLL feedback output. The device operates from a dual voltage supply: 3.3 V for the core logic and 1.8 V for the HSTL outputs. The fully integrated PLL supports an input frequency range of 75 to 287.5 MHz. The output frequencies are configurable.
MPC9990
* * * * * * * * * * * * *
Supports high performance HSTL clock distribution systems Compatible to IA64 processor systems Fully Integrated PLL, differential design Core logic operates from 3.3 V power supply HSTL outputs operate from a 1.8 V supply Programmable frequency by output bank 10 HSTL compatible outputs (two banks) HSTL compatible PLL feedback output HSTL compatible sychronization output (QSYNC) Max. skew of 80 ps within output bank Zero-delay capability: max. SPO (tpd) window of 150 ps LVPECL compatible clock input, LVCMOS compatible control inputs Temperature range of 0 to +70C
LOW VOLTAGE DIFFERENTIAL PECL-HSTL PLL CLOCK DRIVER
FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932
The MPC9990 provides output clock frequencies required for high-performance computer system optimization. The device drives up to 10 differential clock loads within the frequency range of 75 to 287.5 MHz. The 10 outputs are organized in 2 banks of 3 and 7 differential outputs. In the standard configuration the QFB output pair is connected to the FB input pair closing the PLL loop and enabling zero delay operation from the CLK input to the outputs. Bank B outputs are frequency and phase aligned to the CLK input, providing exact copies of the high-speed input signal. Bank A outputs are configured to operate at slower speeds driving the system bus devices. The output frequency ratio of bank A to bank B is adjustable (for available ratios, see "MPC9990 Application: CPU to System Bus Frequency Ratios" on page 2) for system optimization. In a computer application, bank B outputs generate the clock signals for the devices operating at the CPU frequency, while Bank A outputs are configured to drive the clock signals for the devices running at lower speeds (system clock). Four individual frequency ratios are available, providing a high degree of flexibility. The frequency ratios between CPU clock and system clock provided by the MPC9990 are listed in the table "Output configuration" on page 4. The QSYNC output functionality is designed for system synchronization purpose. QSYNC is asserted at coincident rising edges of CPU (bank B and QFB signal) and slower system clock (bank A) outputs (see "QSYNC Phase Relation Diagram" on page 4), providing baseline timing in systems with fractional clocks. The QSYNC output is asserted for one QFB high pulse, centered on the rising QFB output.
CLK 250 MHz QB[0:2] QA[0:6] QSYNC FB QFB CPU clocks System clocks: 250, 200, 187, 125 MHz System synchronization
MPC9990 250 MHz
Figure 1. MPC9990 Application Example
1. In order to minimize output-to-output skew, HSTL outputs of the MPC9990 are generated with an open emitter architecture. For output termination, see "HSTL Output Termination and AC Test Reference" on page 5.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 2002
MPC9990
Bank A QA0 QA0 QA1 QA1 QA2 QA2 QA3 QA3 QA4 QA4 QA5 QA5 QA6 QA6 Bank B QB0 QB0 QB1 QB1 QB2 QB2
CLK CLK FB FB
PD
LPF
VCO
Data Generator
VCO_SEL
ASEL[0:1] BSEL
TEST
Test Mode Control
MR
QFB QFB QSYNC Pulse Control QSYNC QSYNC
OE
Figure 2. MPC9990 Logic Diagram
Table 1: MPC9990 Application: CPU to System Bus Frequency Ratios
QA to QB frequency ratio QA output frequency QB output frequency QA output frequency QB output frequency QA output frequency QB output frequency QA output frequency QB output frequency QA output frequency QB output frequency QA output frequency QB output frequency 1:1 1:2 3:4 4:5 60 75 80 100 100 125 120 150 160 200 200 250 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Output frequencies for CLK = 75 MHz (BSEL=1, VCO_SEL=1) 75 37.5 56.25 75 75 75 Output frequencies for CLK = 100 MHz (BSEL=1, VCO_SEL=1) 100 50 75 100 100 100 Output frequencies for CLK = 125 MHz (BSEL=1, VCO_SEL=1) 125 62.5 93.75 125 125 125 Output frequencies for CLK = 150 MHz (BSEL=1, VCO_SEL=0) 150 75 112.5 150 150 150 Output frequencies for CLK = 200 MHz (BSEL=1, VCO_SEL=0) 200 100 150 200 200 200 Output frequencies for CLK = 250 MHz (BSEL=1 VCO_SEL=0) 250 125 187.5 250 250 250
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TIMING SOLUTIONS
MPC9990
VCCO VCCO VCCO 25 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 QB2 QB2 VCCO QB1 QB1 QB0 QB0 VCCO QFB QFB FB FB CLK Description Differential clock frequency input Differential feedback input Bank A outputs Bank B outputs Synchronization output Differential feedback output pull-down pull-down pull-down pull-down pull-up pull-up Selection of operating frequency range Selection of bank A output frequency Selection of bank B output frequency Selection of PLL operation or TEST mode (PLL bypass) Master reset. Assertion of master reset required on startup Output enable Analog power supply, typical 3.3 V Core power supply, typical 3.3 V Output power supply, typical 1.8 V Output, analog and core logic ground, 0V (VEE) VCC QA3 QA3 QA4 QA4 QA5 QA5 QA6 27 GND QA6 26 CLK
36 QA2 QA2 VCCO QA1 QA1 QA0 QA0 VCCO QSYNC QSYNC GND VCCA 37 38 39 40 41 42 43 44 45 46 47 48
35
34
33
32
31
30
29
28
MPC9990
VCO_SEL
VCC
BSEL
GND
MR
ASEL [0]
ASEL [1]
Figure 3. 48-Lead Package Pinout (Top View) Table 2: Pin configuration
Pin CLK, CLK FB, FB QAn, QAn QBn, QBn QSYNC, QSYNC QFB, QFB VCO_SEL ASEL[0:1] BSEL TEST MR OE VCCA VCC VCCO GND I/O Input Input Output Output Output Output Input Input Input Input Input Input Type LVPECL HSTLL HSTL HSTL HSTL HSTL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Power supply Power supply Power supply Ground Internal resistor CLK: pull-down, CLK: pull-up FB: pull-down, FB: pull-up
TIMING SOLUTIONS
3
TEST
OE
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MPC9990
Table 3: Output Frequency Relationship for an Example Configuration
ASEL[0] 0 0 1 1 0 0 1 1 ASEL[1] 0 1 0 1 0 1 0 1 BSEL 0 0 0 0 1 1 1 1 f QAn f QBn f QFB CLK CLK CLK CLK CLK CLK CLK CLK QSYNC L enabled enabled enabled L enabled enabled enabled CLK CLK
B2 CLK x 3 B 4 CLK x 4 B 5
CLK
B2 CLK x 3 B 4 CLK x 4 B 5
CLK CLK CLK CLK CLK
B2 CLK x 3 B 4 CLK x 4 B 5
CLK 0 PLL enabled Reset (Internal logic and PLL)
CLK
Table 4: Function Table (Controls)
Control Pin TEST MR OE VCO_SEL 1 PLL bypassed (Static test mode) Normal operation mode Outputs enabled Low frequency operation (VCO frequency range from 300 to 575 MHz)
Outputs disabled (QX = L, QX = H), except QFB, QFB High frequency operation (VCO frequency range from 600 to 1150 MHz)
QAx
QFB
QSYNC
Figure 4. QSYNC Phase Relation Diagram The MPC9990 QSYNC output is designed for system synchronization purpose. The output frequency relationship between the QA-bank and the QFB-output (see table 3) controls the status of QSYNC. The internal QSYNC pulse circuitry is enabled if the frequency relationship between the QA-banks and QFB is not an integer multiple of each other (fQA:fQFB = 1:2, 3:4 and 4:5) (see table 3). QSYNC is asserted (logic high pulse) centered on coincident rising edges at the QA-bank outputs and QFB. The QSYNC output transitions at the falling edges of QFB (assertion at the last falling edge of QFB prior to the coincident edge event, Table 5: ABSOLUTE MAXIMUM RATINGS*
Symbol VCCA VCC VCCO VIN IIN IOUT TS Characteristics Analog power supply Core power supply Output power supply Input voltage Input current Output current Storage temperature Min -0.5 -0.5 -0.5 -0.5 -1.0 -50 -50 Max 3.6 3.6 3.6 VCC + 0.3 1.0 50 150 Units V V V V mA mA C Condition
deassertion at the next falling edge of QFB). The QSYNC output pulse width is equal to period of the QFB output (see figure 4, also see the max. skew specification QFB to QSYNC). If BSEL=1 and the PLL is frequency and phase locked, QSYNC output pulses occur centered on coincident edges between the QA-bank and QB-bank outputs (offset by the feedback path delay) due to the fixed relationship between CLK, QFB and QB bank outputs.
DC DC
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
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MPC9990
Table 6: DC CHARACTERISTICS (VCC = VCCA = 3.3 V 5%, VCCO = 1.7 to 2.1V, TA = 0 to 70C)
Symbol HSTL I/Oa VCCO VIN VDIF VCM VOH VOL Output power supply Input voltage (FB) 1.7 -0.3 0.2 0.64 1.0 0 VX+0.4 VX-0.4 1.8 2.1 1.45 1.75 0.9 1.4 0.4 1.7 -0.3 0.2 0.68 1.0 0 VX+0.4 VX-0.4 1.8 2.1 1.45 1.75 0.9 1.4 0.4 1.7 -0.3 0.2 0.68 1.0 0 VX+0.4 VX-0.4 1.8 2.1 1.45 1.75 1.0 1.4 0.4 V V V V V Differential Differential Characteristics Min 0 C Typ Max Min 25 C Typ Max Min 70 C Typ Max Unit Condition
Differential input voltageb (FB) Common mode input voltagec (FB) Output high voltage Output low voltage
LVPECL I/O VCC VCCA VPP VCMR Power supply voltage (core) Power supply voltage (PLL) Peak-to-peak input voltage CLK, PCLK 3.135 3.135 3.3 3.3 3.465 3.465 3.135 3.135 3.3 3.3 3.465 3.465 3.135 3.135 3.3 3.3 3.465 3.465 V V
500
1000
500
1000
500
1000 VCC0.6 150 141 15 180 20
mV V A mA mA
Common Mode Ranged CLK, PCLK VCC-1.4 Input high current Power supply current (core) Power supply current (PLL) 141 15
VCC- VCC-1.4 0.6 150 180 20 141 15
VCC- VCC-1.4 0.6 150 180 20
IIH ICC ICCA
LVCMOS Inputs VIH VIL II a. b. c. d. e. Input high voltage Input low voltage Input current 2 0 VCC 0.8 100 2 0 VCC 0.8 100 2 0 VCC 0.8 100 V V A
See "HSTL Differential Input Levels" in Figure 5. VDIF specifies the input differential voltage. VCM is the maximum allowable range of VTR - ((VTR - VCP)/2). VTR is true input signal, VCP is its complementary input signal. VCMR is the difference from VCC and the crosspoint of the differential input signal. Normal operation is obtained when the "high" input is within the VCMR range and the input swing lies within the VPP specification. LVPECL input level specifications will vary 1:1 with VCC. VCCO VTR VDIF VCMR VCP VEE VX
Figure 5. HSTL Differential Input Levels
Z = 50 Differential Pulse Generator Z = 50W RT = 50 VTT = GND Z = 50
MPC9990
RT = 50 VTT = GND
Figure 6. HSTL Output Termination and AC Test Reference
TIMING SOLUTIONS
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MPC9990
Table 7: AC CHARACTERISTICS (VCCI = VCCA = 3.3 V 5%, VCCO = 1.7 to 2.1 V, TA = 0 to 70C)a
Symbol fIN Characteristics Min Input frequencyb for VCO_SEL = 0 (high range) 1:1 ratio, ASEL=00 1:2 ratio, ASEL=01 3:4 ratio, ASEL=10 4:5 ratio, ASEL=11 Input frequencyb for VCO_SEL = 1 (low range) 1:1 ratio, ASEL=00 1:2 ratio, ASEL=01 3:4 ratio, ASEL=10 4:5 ratio, ASEL=11 VCO frequency VCO_SEL = 0 (high range) VCO_SEL = 1 (low range) Output frequencyc Static phase offset, tPD between CLK and FB VCO_SEL=0 VCO_SEL=1 Output duty cycle Differential output skew tSK(OB) within bankd tSK(O) single frequencye tSK(O) multiple frequencyf tSK(OFB) QFB to QA0-6 for ASEL=00 for ASEL=01 for ASEL=10 for ASEL=11 tSK(O) QFB to QSYNC Minimum input swing Common mode range 0C Typ Max Min 25C Typ Max Min 70C Typ Unit Condition Max
150.0 150.0 200.0 150.0
287.5 287.5 287.5 287.5
150.0 150.0 200.0 150.0
287.5 287.5 287.5 287.5
150.0 150.0 200.0 150.0
287.5 287.5 287.5 287.5
MHz MHz MHz MHz
600 < fVCO < 1150 MHz
75.0 75.0 100.0 75.0 600 300
143.75 75.0 143.75 75.0 191.67 100.0 143.75 75.0 1150 575 287.5 600 300
150.0 150.0 191.6 150.0 1150 575 287.5
75.0 75.0 100.0 75.0 600 300
150.0 150.0 191.6 150.0 1150 575 287.5
MHz MHz MHz MHz MHz MHz MHz
300 < fVCO < 575 MHz
fVCO
fOUT SPO
DC tSK
-200 -250 45
50
-50 -50 55 80 100 250
-200 -250 45
50
-50 -50 55 80 100 250
-200 -250 45
50
-50 -50 55 80 100 250 -115 -175 -115 -135 500 1 VCC-0 .4
ps ps % ps ps ps ps ps ps ps ps V V Diff. HSTL outputs
VPPg VCMR VDIF,OUT VX
85 25 135 65 -500 0.5 1
Minimum output swing 0.6 0.8 0.8 0.8 V HSTL Differential output crosspoint 0.64 1.0 V HSTL voltage tJIT(CC) Cycle-to-cycle jitter fVCO >= 750 MHz 75 75 75 ps fVCO < 750 MHz 125 125 125 ps tJIT(PER) Period Jitter VCO_SEL=0 75 75 75 ps VCO_SEL=1 125 125 125 ps tJIT(IO) I/O Phase Jitter RMS (1 ) 600 MHz< fVCO <750 MHz 50 50 50 ps 750 MHz< fVCO <900 MHz 40 40 40 ps 900 MHz< fVCO <1150 MHz 30 30 30 ps BW PLL bandwidth 1:1 ratio, ASEL=00 0.6-1.0 0.6-1.0 0.6-1.0 MHz 1:2 ratio, ASEL=01 0.6-1.0 0.6-1.0 0.6-1.0 MHz 3:4 ratio, ASEL=10 1.0-1.2 1.0-1.2 1.0-1.2 MHz 4:5 ratio, ASEL=11 0.6-1.0 0.6-1.0 0.6-1.0 MHz tr, tf Output transition rate 0.8 2 0.8 2 0.8 2 V/ns tLock PLL lock time 10 10 10 ms a. Refer to "HSTL Output Termination and AC Test Reference" for AC test conditions in Figure 6. b. The input frequency for the output configurations are limited by the VCO frequency range and the feedback divider. c. fOUT at which output-to-output skew, VX and DC specification are still meet. fOUT is primary a function of fIN and the input-to-output frequency ratio (M:N). d. Output skew within bank A outputs (QA0-QA6) and output skew within bank B outputs (QB0-QB2). e. Output skew within all outputs (QA0-QA6, QB0-QB2) running at the same output frequency. f. Output skew within all outputs (QA0-QA6, QB0-QB2) running at any output frequency. g. VPP specifies the minimum input differential voltage required for switching.
85 -115 25 -175 135 -115 65 -135 -500 500 1 0.5 VCC-0. 1 4 0.6 0.9 0.68
85 -115 25 -175 135 -115 65 -135 -500 500 1 0.5 VCC-0 1 .4 0.6 0.9 0.68
LVPECL LVPECL
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TIMING SOLUTIONS
MPC9990
APPLICATIONS INFORMATION
Using the MPC9990 in zero-delay applications Nested clock trees are typical applications for the MPC9990 Designs using the MPC9990 as PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from static fanout buffers. The external feedback option of the MPC9990 clock driver allows for its use as a zero delay buffer. By using the differential QFB output pair as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input (CLK) and any output. This effective delay consists of the static phase offset (SPO), I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of part-to-part skew The MPC9990 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9990 are connected together, the maximum overall timing uncertainty from the common CLK input to any output is: Due to the statistical nature of I/O jitter a rms value (1 s) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8.
Table 8: Confidence Facter CF
CF 1s 2s 3s 4s 5s 6s Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999
The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3s) and single frequency configuration is assumed, resulting in a worst case timing uncertainty from input to any output of -495 ps to +245 ps relative to CLK.
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT(PER) + tJIT() CF
This maximum timing uncertainty consist of 4 components: static phase offset (SPO), output skew, feedback board trace delay and I/O phase and period jitter. The output skew (tSK(O)) specification of the MPC9990 is different for single or for dual frequency bank configurations. :
CLKCommon
tSK(PP) = [-200ps...-50ps] + [-100ps...100ps] + [-75ps...75ps] + [(30ps@ -3)...(30ps@ 3)] + tPD, LINE(FB) tSK(PP) = [-495ps...+245ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure 8. "Max. I/O Jitter versus frequency" can be used for a more precise timing performance analysis. The number for the I/O jitter at a specific frequency can be substituted for the more general datasheet specification number:
-t()
tPD,LINE(FB)
FBDevice 1
tJIT()
Any QDevice 1
+tSK(O) +t()
FBDevice2
tJIT()
Any QDevice 2 Max. skew
+tSK(O) tSK(PP)
Complementary signals are not shown. Signal references level is the differential voltage crosspoint VX
Figure 7. MPC9990 max. device-to-device skew
Figure 8. Max. I/O Jitter versus frequency
TIMING SOLUTIONS
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MPC9990
Power Supply Filtering The MPC9990 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply. Random noise on the VCCA power supply impacts the device AC characteristics, for instance I/O jitter. The MPC9990 provides separate power supplies for the output buffers (VCCO) and the phase-locked loop (VCCA) of the device. RF 9 W for VCC = 3.3V
RF 3.3V5% CF 6.8 F 10 nF VCCA MPC9990 VCC 2 33 ... 100 nF +0.3 V 1.8V -0.1 V VCCO 7 33 ... 100 nF Place VCCA filter and VCCO, VCC bypass capacitors as close as possible to the device
have a maximum resistance of 9 to meet the voltage drop criteria. The minimum resistance for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater 40 dB for noise whose spectral content is above 300 kHz. In the example RC filter shown in Figure 9. "Recommended Power Supply Filter", the filter cut-off frequency is 16.3 kHz and the noise attenuation at 300 kHz is approximately 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown (6.8 F || 10 nF) ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9990 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds, internal voltage regulation and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Recommended Power-up Sequence The MPC9990 does not require any special supply ramp sequence in case the system prorides all supply voltages (3.3V and 1.8V) at the same time. The reference clock signal (CLK, CLK) can be applied any time during or after the power up sequence if VIN is smaller or equal VCC during the voltage transition. Following are guidelines for the MPC9990 power-up sequence in case the 3.3V and 1.8V voltage supply cannot be applied at the same time:
W
Figure 9. Recommended Power Supply Filter The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is difficult to minimize noise on the power supplies a second level of isolation may be required. A simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9990. Figure 9. illustrates a recommended power supply low-pass frequency filter scheme. The MPC9990 VCO frequency and phase stability is most susceptible to noise with spectral content in the 300 kHz to 3 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. The maximum voltage drop on VCCA that can be tolerated is 135 mV with respect to VCC = 3.3V 5%, resulting in a lowest allowable supply voltage for VCCA equal to 2.835 V. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 11 mA (15 mA maximum), assuming that the minimum of 3.0V (VCC=3.3V-5%-0.135V) must be maintained on the VCCA pin. The resistor RF shown in Figure 9. "Recommended Power Supply Filter" should
* HSTL output supply voltage VCCO must be powered up to
the specified voltage range before or at the same time as VCC. VCCA can be powered up before, at the same time or after VCC and VCCO. At the time the power supplies are powered up, the device should be reset (MR=0). Apply the clock input signals to the PLL (CLK, CLK) after all power supplies are stable. Then, MR can be deasserted (MR=1). This will release the internal PLL which will attempt to lock. The time from MR deassertion to PLL lock will be specified by the PLL lock time tLock. After the PLL achieved lock, the AC characteristics are valid. Outputs can be enabled by OE any time. QFB is not affected by OE and the PLL can achieve lock even if OE is tied high (OE = 1, disable).
* *
* *
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TIMING SOLUTIONS
MPC9990
Calculating the Power Consumption The total power dissipated in the MPC9990 (PTOT) can be represented by this formula: PTOT = PCORE + (N POUTPUT) where PCORE is the core and PLL power consumption (VCC and VCCA pins), POUTPUT is the power consumption of the output drivers (VCCO pins) and N is the number of terminated outputs: PCORE = VCC ICC POUTPUT = (VCCO - VOUT) [(VX - VTT) / RTERM] ICC is the current consumption of the core including the current consumption of the PLL. VX represents the average output voltage for a 50% duty cycle output signal. VX and ICC can be obtained from the specification values. VCC, VCCO, and the termination resistor RTERM are application-dependent. Table 9: Example Calculation
Term VCC ICCa PCORE VCCO VOUTb VX VTT RTERM POUTPUT N PTOT Value (worst case) 3.3V+5% 180 mA 624 mW 2.1V 0.68V 0.9V 0V 50 25.5 mW 24 1237 mW Value (typical case) 3.3V 141 mA 465 mW 1.8V 0.8V 0.8V 0V 50 16 mW 24 849 mW
a. ICC already includes ICCA. b. The value for VOUT is average output voltage assuming the duty cycle of the output is approx. 50%.
TIMING SOLUTIONS
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MPC9990
QX VX QX QY VX QY tSK(O), tSK(OB) The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay path within a single device (tSK(O)) or within a single output bank (tSK(OB)) FB t() CLK FB VX CLK VX
Figure 11. Propagation delay (t, static phase offset, SPO) test reference
Figure 10. Output-to-output Skew tSK(O), tSK(OB)
QX VX QX tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
CLK CLK VX VX
FB TJIT ) = |T0 -T1 mean|
The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles, measured at the FB signal (only true signal shown)
Figure 12. Output Duty Cycle (DC)
Figure 13. I/O Jitter
TN
TN+1
TJIT(CC) = |TN -TN+1 |
T0
TJIT(PER) = |TN -1/f0 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs, measured at an output (only true signal shown)
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles (only true signal shown)
Figure 14. Cycle-to-cycle Jitter
Figure 15. Period Jitter
VOH 80% 20% VOL tF tR
Figure 16. Output Transition Time Test Reference
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MPC9990
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 932-03 ISSUE F
4X
0.200 AB T-U Z 9 A1
48 37
A
DETAIL Y
P
1
36
T B B1
12 25
U V AE V1 AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3.DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4.DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8.MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9.EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0_ 7_ 12 _REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AD AC
BASE METAL
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M_
TOP & BOTTOM
R
GAUGE PLANE
0.080
SECTION AE-AE
TIMING SOLUTIONS
EEE CCC EEE CCC EEE CCC
F D
M
C
E
AC T-U Z H DETAIL AD AA W K L_
11
0.250
N
J
MOTOROLA
MPC9990
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2002.
How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
MOTOROLA
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MPC9990/D TIMING SOLUTIONS

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